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? semiconductor components industries, llc, 2013 february, 2013 ? rev. 2 1 publication order number: ncv890100/d ncv890100 1.2a, 2mhz automotive buck switching regulator the ncv890100 is a fixed ? frequency, monolithic, buck switching regulator intended for automotive, battery ? connected applications that must operate with up to a 36v input supply. the regulator is suitable for systems with low noise and small form factor requirements often encountered in automotive driver information systems. the ncv890100 is capable of converting the typical 4.5 v to 18 v automotive input voltage range to outputs as low as 3.3 v at a constant switching frequency above the sensitive am band, eliminating the need for costly filters and emi countermeasures. the ncv890100 also provides several protection features expected in automotive power supply systems such as current limit, short circuit protection, and thermal shutdown. in addition, the high switching frequency produces low output voltage ripple even when using small inductor values and an all ? ceramic output filter capacitor ? forming a space ? efficient switching regulator solution. features ? internal n ? channel power switch ? low v in operation down to 4.5 v ? high v in operation to 36 v ? withstands load dump to 40 v ? 2 mhz free ? running switching frequency ? logic level enable input can be directly tied to battery ? 1.4 a (min) cycle ? by ? cycle peak current limit ? short circuit protection enhanced by frequency foldback ? 1.75% output voltage tolerance ? output voltage adjustable down to 0.8 v ? 1.4 millisecond internal soft ? start ? thermal shutdown (tsd) ? low shutdown current ? wettable flanks dfn ? ncv prefix for automotive and other applications requiring unique site and control change requirements; aec ? q100 qualified and ppap capable ? these devices are pb ? free and are rohs compliant applications ? audio ? infotainment ? safety ? vision systems ? instrumentation dfn8 case 506by marking diagrams a = assembly location l = wafer lot y = year w = work week = pb ? free device http://onsemi.com (*note: microdot may be in either location) v8901 00 alyw see detailed ordering and shipping information in the package dimensions section on page 14 of this data sheet. ordering information 1 soic ? 8 ep case 751ac 1 8 1 8 ncv890100 alywx
ncv890100 http://onsemi.com 2 vin drv gnd en sw bst fb comp vin en vout cin cbst dbst dfw rcomp ccomp cout l1 cdrv ncv890100 rfb2 rfb1 1 2 3 45 6 7 8 figure 1. typical application
ncv890100 http://onsemi.com 3 figure 2. ncv890100 block diagram vin drv gnd en sw bst fb comp vin enable vout cin cbst dbst dfw rcomp ccomp cout l1 cdrv pwm logic s oscillator soft ? start reset 3.3 v reg voltages monitors tsd + + ? off on + ? + + 1.2 a
ncv890100 http://onsemi.com 4 maximum ratings rating symbol value unit min/max voltage vin ? 0.3 to 40 v max voltage vin to sw 40 v min/max voltage sw ? 0.7 to 40 v min voltage sw ? 20ns ? 3.0 v min/max voltage bst ? 0.3 to 40 min/max voltage bst to sw ? 0.3 to 3.6 v min/max voltage on en ? 0.3 to 40 v min/max voltage comp ? 0.3 to 2 v min/max voltage fb ? 0.3 to 18 v min/max voltage drv ? 0.3 to 3.6 v thermal resistance, 3x3 dfn junction ? to ? ambient* r ja 50 c/w thermal resistance, soic ? 8 ep junction ? to ? ambient* r ja 40 c/w storage temperature range ? 55 to +150 c operating junction temperature range t j ? 40 to +150 c esd withstand voltage human body model machine model charge device model v esd 2.0 200 >1.0 kv v kv moisture sensitivity, dfn8 msl level 1 moisture sensitivity, soic ? 8 ep msl level 2 peak reflow soldering temperature 260 c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. *mounted on 1 sq. in. of a 4 ? layer pcb with 1 oz. copper thickness. recommended operating conditions: rating value unit v in range 4.5 to 36 v ambient temperature range ? 40 to 105 c
ncv890100 http://onsemi.com 5 figure 3. pin connections 1 vin sw 2 drv 3 4 gnd bst 8 7 fb (top view) 5 en 6 comp 1 vin sw 2 drv 3 4 gnd bst 8 7 fb (top view) 5 en 6 comp pin function descriptions pin no. symbol description 1 vin input voltage from battery. place an input filter capacitor in close proximity to this pin. 2 drv output voltage to provide a regulated voltage to the power switch gate driver. 3 gnd battery return, and output voltage ground reference. 4 en this ttl compatible enable input allows the direct connection of battery as the enable signal. grounding this input stops switching and reduces quiescent current draw to a minimum. 5 comp error amplifier output, for tailoring transient response with external compensation components. 6 fb feedback input pin to program output voltage, and detect pre ? charged or shorted output conditions. 7 bst bootstrap input provides drive voltage higher than vin to the n ? channel power switch for optimum switch r ds(on) and highest efficiency. 8 sw switching node of the regulator. connect the output inductor and cathode of the freewheeling diode to this pin. exposed pad connect to pin 3 (electrical ground) and to a low thermal resistance path to the ambient temperature environment.
ncv890100 http://onsemi.com 6 electrical characteristics (v in = 4.5 v to 28 v, v en = 5 v, v bst = v sw + 3.0 v, c drv = 0.1 f, min/max values are valid for the temperature range ? 40 c t j 150 c unless noted otherwise, and are guaranteed by test, design or statistical correlation.) parameter symbol conditions min typ max unit quiescent current quiescent current, shutdown i qsd v in = 13.2 v, v en = 0 v, t j = 25 c 5 a quiescent current, enabled i qen v in = 13.2 v 3 ma undervoltage lockout ? vin (uvlo) uvlo start threshold v uvlstt v in rising 4.1 4.5 v uvlo stop threshold v uvlstp v in falling 3.9 4.4 v uvlo hysteresis v uvlohy 0.1 0.2 v enable (en) logic low v enlo 0.8 v logic high v enhi 2 v input current i en 8 30 a soft ? start (ss) soft ? start completion time t ss 0.8 1.4 2.0 ms voltage reference fb pin voltage during regulation v fbr comp shorted to fb 0.786 0.8 0.814 v error amplifier fb bias current i fbbias v fb = 0.8 v 0.25 1 a transconductance g m g m(hv) v comp = 1.3 v 4.5 v < v in < 18 v 20 v < v in < 28 v 0.6 0.3 1 0.5 1.5 0.75 mmho output resistance r out 1.4 m comp source current limit i source v fb = 0.63 v, v comp = 1.3 v 4.5 v < v in < 18 v 20 v < v in < 28 v 75 40 a comp sink current limit i sink v fb = 0.97 v, v comp = 1.3 v 4.5 v < v in < 18 v 20 v < v in < 28 v 75 40 a minimum comp voltage v cmpmin v fb = 0.97 v 0.2 0.7 v oscillator frequency f sw f sw(hv) 4.5 < v in < 18 v 20 v < v in < 28 v 1.8 0.9 2.0 1.0 2.2 1.1 mhz vin frequency foldback monitor frequency foldback threshold v in rising v in falling v fldup v flddn v fb = 0.63 v 18.4 18 20 19.8 v frequency foldback hysteresis v fldhy 0.2 0.3 0.4 v slope compensation ramp slope (note 1) (with respect to switch current) s ramp s ramp(hv) 4.5 < v in < 18 v 20 v < v in < 28 v 0.7 0.25 1.3 0.6 a/ s 1. not tested in production. limits are guaranteed by design.
ncv890100 http://onsemi.com 7 electrical characteristics (v in = 4.5 v to 28 v, v en = 5 v, v bst = v sw + 3.0 v, c drv = 0.1 f, min/max values are valid for the temperature range ? 40 c t j 150 c unless noted otherwise, and are guaranteed by test, design or statistical correlation.) parameter unit max typ min conditions symbol power switch on resistance r dson v bst = v sw + 3.0 v 650 m leakage current vin to sw i lksw v en = 0 v, v sw = 0, v in = 18 v 10 a minimum on time t onmin measured at sw pin 45 70 ns minimum off time t offmin measured at sw pin at f sw = 2 mhz (normal) at f sw = 500 khz (max duty cycle) 30 30 50 70 ns peak current limit current limit threshold i lim 1.4 1.55 1.7 a short circuit frequency foldback lowest foldback frequency lowest foldback frequency ? high v in hiccup mode f swaf f swafhv f swhic v fb = 0 v, 4.5 v < v in < 18 v v fb = 0 v, 20 v < v in < 28 v v fb = 0 v 400 200 24 500 250 32 600 300 40 khz gate voltage supply (drv pin) output voltage v drv 3.1 3.3 3.5 v drv por start threshold v drvstt 2.7 2.9 3.05 v drv por stop threshold v drvstp 2.5 2.8 3.0 v drv current limit i drvlim v drv = 0 v 16 45 ma output precharge detector threshold voltage v ssen 20 35 50 mv thermal shutdown activation temperature (note 1) t sd 150 190 c hysteresis (note 1) t hys 5 20 c 1. not tested in production. limits are guaranteed by design.
ncv890100 http://onsemi.com 8 typical characteristics curves 0 1 2 3 4 5 6 7 8 ? 50 ? 25 0 25 50 75 100 125 150 t j . junction temperature ( c) i qsd . shutdown quiescent current ( a) figure 4. shutdown quiescent current vs. junction temperature v in = 13.2 v 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 ? 50 ? 25 0 25 50 75 100 125 150 t j . junction temperature ( c) i qen . enabled quiescent current (ma) figure 5. enabled quiescent current vs. junction temperature 3.9 4.0 4.1 4.2 4.3 4.4 4.5 4.6 4.7 ? 50 ? 25 0 25 50 75 100 125 150 t j . junction temperature ( c) v uvlstt . uvlo start threshold (v) figure 6. uvlo start threshold vs. junction temperature 3.7 3.8 3.9 4.0 4.1 4.2 4.3 4.4 4.5 4.6 ? 50 ? 25 0 25 50 75 100 125 150 t j . junction temperature ( c) v uvlstp . uvlo stop threshold (v) figure 7. uvlo stop threshold vs. junction temperature 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 ? 50 ? 25 0 25 50 75 100 125 150 t j . junction temperature ( c) t ss . soft ? start duration (ms) figure 8. soft ? start duration vs. junction temperature 0.75 0.76 0.77 0.78 0.79 0.80 0.81 0.82 0.83 0.84 0.85 ? 50 ? 25 0 25 50 75 100 125 150 v fbr . fb regulation voltage (v) t j . junction temperature ( c) figure 9. fb regulation voltage vs. junction temperature
ncv890100 http://onsemi.com 9 typical characteristics curves 0.2 0.4 0.6 0.8 1.0 1.2 1.4 ? 50 ? 25 0 25 50 75 100 125 150 t j . junction temperature ( c) g m . error amplifier transconductance (ms) figure 10. error amplifier transconductance vs. junction temperature v in = 4.5 v v in = 28 v 20 30 40 50 60 70 80 90 100 ? 50 ? 25 0 25 50 75 100 125 150 t j . junction temperature ( c) i source . error amplifier sourcing current ( a) figure 11. error amplifier max sourcing current vs. junction temperature v in = 4.5 v v in = 28 v 20 30 40 50 60 70 80 90 100 ? 50 ? 25 0 25 50 75 100 125 150 t j . junction temperature ( c) i sink . error amplifier sinking current ( a) figure 12. error amplifier max sinking current vs. junction temperature v in = 4.5 v v in = 28 v 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 ? 50 ? 25 0 25 50 75 100 125 150 t j . junction temperature ( c) f sw . oscillator freqency (mhz) figure 13. oscillator frequency vs. junction temperature v in = 13.2 v v in = 28 v 18.2 18.4 18.6 18.8 19.0 19.2 19.4 19.6 ? 50 ? 25 0 25 50 75 100 125 150 t j . junction temperature ( c) v fldup . v flddn , freq. foldback threshold (v) figure 14. rising frequency foldback threshold vs. junction temperature figure 15. power switch r ds(on) vs. junction temperature v fldup v flddn 0 100 200 300 400 500 600 700 800 900 ? 50 ? 25 0 25 50 75 100 125 0 15 r ds(on) . power switch on resistance (m ) t j . junction temperature ( c)
ncv890100 http://onsemi.com 10 typical characteristics curves figure 16. minimum on time vs. junction temperature figure 17. minimum off time vs. junction temperature 40 45 50 55 60 65 70 75 80 ? 50 ? 25 0 25 50 75 100 125 150 t onmin . minimum time (ns) t j . junction temperature ( c) figure 18. current limit threshold vs. junction temperature 35 40 45 50 55 60 65 70 75 ? 50 ? 25 0 25 50 75 100 125 150 t offmin . minimum time (ns) t j . junction temperature ( c) figure 19. short ? circuit foldback frequency vs. junction temperature 1.40 1.45 1.50 1.55 1.60 1.65 1.70 ? 50 ? 25 0 25 50 75 100 125 150 i lim . minimum time (ns) t j . junction temperature ( c) figure 20. hiccup mode switching frequency vs. junction temperature 200 250 300 350 400 450 500 550 600 ? 50 ? 25 0 25 50 75 100 125 150 f swaf . foldback mode switching frequency (khz) t j . junction temperature ( c) figure 21. drv voltage vs. junction temperature v in = 4.5 v v in = 28 v 24 26 28 30 32 34 36 38 40 ? 50 ? 25 0 25 50 75 100 125 150 f swhc . hiccup mode freuqncy (khz) t j . junction temperature ( c) 3.10 3.15 3.20 3.25 3.30 3.35 3.40 3.45 3.50 ? 50 ? 25 0 25 50 75 100 125 150 v drv . drv voltage (v) t j . junction temperature ( c) i drv = 0 ma i drv = 16 ma
ncv890100 http://onsemi.com 11 typical characteristics curves figure 22. drv reset threshold vs. junction temperature 2.5 2.6 2.7 2.8 2.9 3.0 3.1 ? 50 ? 25 0 25 50 75 100 125 150 v drvstt . v drvstp , drv reset thresholds (v) t j . junction temperature ( c) figure 23. drv current limit vs. junction temperature v drvstt v drvstp 21 22 23 24 25 26 27 28 29 30 ? 50 ? 25 0 25 50 75 100 125 150 i drvlim . drv current limit (ma) 20 25 30 35 40 45 50 55 ? 50 ? 25 0 25 50 75 100 125 150 v ssen . output precharge detector threshold (v) t j . junction temperature ( c) figure 24. output precharge detector threshold vs. junction temperature t j . junction temperature ( c)
ncv890100 http://onsemi.com 12 general information input voltage an undervoltage lockout (uvlo) circuit monitors the input, and inhibits switching and resets the soft ? start circuit if there is insufficient voltage for proper regulation. the ncv890100 can regulate a 3.3 v output with input voltages above 4.5 v and a 5.0 v output with an input above 6.5 v. the ncv890100 withstands input voltages up to 40 v. to limit the power lost in generating the drive voltage for the power switch, the switching frequency is reduced by a factor of 2 when the input voltage exceeds the v in frequency foldback threshold v fldup (see figure 25). frequency reduction is automatically terminated when the input voltage drops back below the v in frequency foldback threshold v flddn . 41820 36 vin (v) 1 2 fsw (mhz) figure 25. ncv890100 switching frequency reduction at high input voltage enable the ncv890100 is designed to accept either a logic level signal or battery voltage as an enable signal. en low induces a ?sleep mode? which shuts off the regulator and minimizes its supply current to a couple of a typically (i qsd ) by disabling all functions. upon enabling, voltage is established at the drv pin, followed by a soft ? start of the switching regulator output. soft ? start upon being enabled or released from a fault condition, and after the drv voltage is established, a soft ? start circuit ramps the switching regulator error amplifier reference voltage to the final value. during soft ? start, the average switching frequency is lower than its normal mode value (typically 2 mhz) until the output voltage approaches regulation. error amplifier the error amplifier is a transconductance type amplifier. the output voltage of the error amplifier controls the peak inductor current at which the power switch shuts off. the current mode control method employed by the ncv890100 allows the use of a simple, t ype ii compensation to optimize the dynamic response according to system requirements. slope compensation a fixed slope compensation signal is generated internally and added to the sensed current to avoid increased output voltage ripple due to bifurcation of inductor ripple current at duty cycles above 50%. the fixed amplitude of the slope compensation signal requires the inductor to be greater than a minimum value, depending on output voltage, in order to avoid sub ? harmonic oscillations. for 3.3 v and 5 v output voltages, the recommended inductor value is 4.7 h. short circuit frequency foldback during severe output overloads or short circuits, the ncv890100 automatically reduces its switching frequency. this creates duty cycles small enough to limit the peak current in the power components, while maintaining the ability to automatically reestablish the output voltage if the overload is removed. if the current is still too high after the switching frequency folds back to 500 khz, the regulator enters an auto ? recovery burst mode that further reduces the dissipated power. current limiting due to the ripple on the inductor current, the average output current of a buck converter is lower than the peak current setpoint of the regulator. figure 26 shows ? for a 4.7 h inductor ? how the variation of inductor peak current with input voltage affects the maximum dc current the ncv890100 can deliver to a load. figure 26. ncv890100 load current capability with 4.7 h inductor 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 0 5 10 15 20 25 30 35 40 input voltage (v) minimum current limit (a) (5 v out ) (3.3 v out )
ncv890100 http://onsemi.com 13 bootstrap at the drv pin an internal regulator provides a ground ? referenced voltage to an external capacitor (c drv ), to allow fast recharge of the external bootstrap capacitor (c bst ) used to supply power to the power switch gate driver. if the voltage at the drv pin goes below the drv uvlo threshold v drvstp , switching is inhibited and the soft ? start circuit is reset, until the drv pin voltage goes back up above v drvstt . in order for the bootstrap capacitor to stay charged, the switch node needs to be pulled down to ground regularly. in very light load condition, the ncv890100 skips switching cycles to ensure the output voltage stays regulated. when the skip cycle repetition frequency gets too low, the bootstrap voltage collapses and the regulator stops switching. practically, this means that the ncv890100 needs a minimum load to operate correctly: to cover all conditions of input voltage and temperature, this minimum load is 8 ma. output precharge detection prior to soft ? start, the fb pin is monitored to ensure the sw voltage is low enough to have charged the external bootstrap capacitor (c bst ). if the fb pin is higher than v ssen , restart is delayed until the output has discharged. thermal shutdown a thermal shutdown circuit inhibits switching, resets the soft ? start circuit, and removes drv voltage if internal temperature exceeds a safe level. switching is automatically restored when temperature returns to a safe level. minimum dropout voltage when operating at low input voltages, two parameters play a major role in imposing a minimum voltage drop across the regulator: the minimum off time (that sets the maximum duty cycle), and the on state resistance. when operating in continuous conduction mode (ccm), the output voltage is equal to the input voltage multiplied by the duty ratio. because the ncv890100 needs a sufficient bootstrap voltage to operate, its duty cycle cannot be 100%: it needs a minimum off time (t offmin ) to periodically re ? fuel the bootstrap capacitor c bst . this imposes a maximum duty ratio d max = 1 ? t offmin .f sw(min) , with the switching frequency being folded back down to f sw(min) = 500 khz to keep regulating at the lowest input voltage possible. the drop due to the on ? state resistance is simply the voltage drop across the switch resistance r dson at the given output current: v swdrop = i out .r dson . which leads to the maximum output voltage in low vin condition: v out = d max .v in(min) ? v swdrop exposed pad the exposed pad (epad) on the back of the package must be electrically connected to the electrical ground (gnd pin) for proper, noise ? free operation. design methodology the ncv890100 being a fixed ? frequency regulator with the switching element integrated, is optimized for one value of inductor. this value is set to 4.7 h, and the slope compensation is adjusted for this inductor. the only components left to be designed are the input and output capacitor and the freewheeling diode. output capacitor: the minimum output capacitor value can be calculated based on the specification for output voltage ripple: c out min i l 8 v out f sw (eq. 1) with ? i l the inductor ripple current: i l v out 1 v out v in l f sw (eq. 2) ? v out the desired voltage ripple. however, the esr of the output capacitor also contributes to the output voltage ripple, so to comply with the requirement, the esr cannot exceed r esrmax : r esr max v out l f sw v out 1 v out v in (eq. 3) finally, the output capacitor must be able to sustain the ac current (or rms ripple current): i outac i l 23 (eq. 4) typically, with the recommended 4.7 h inductor, two ceramic capacitors of 10 f each in parallel give very good results. freewheeling diode: the diode must be chosen according to its maximum current and voltage ratings, and to thermal considerations. as far as max ratings are concerned, the maximum reverse voltage the diode sees is the maximum input voltage (with some mar gin in case of ringing on the switch node), and the maximum forward current the peak current limit of the ncv890100, i lim . the power dissipated in the diode is p dloss : p dloss i out 1 v out v in v f i drms r d (eq. 5) with: ? i out the average (dc) output current ? v f the forward voltage of the diode ? i drms the rms current in the diode:
ncv890100 http://onsemi.com 14 i drms ( 1 d ) i out 2 i l 2 12 (eq. 6) ? r d the dynamic resistance of the diode (extracted from the v/i curve of the diode in its datasheet). then, knowing the thermal resistance of the package and the amount of heatsinking on the pcb, the temperature rise corresponding to this power dissipation can be estimated. input capacitor: the input capacitor must sustain the rms input ripple current i inac : i inac i l 2 d 3 (eq. 7) it can be designed in combination with an inductor to build an input filter to filter out the ripple current in the source, in order to reduce emi conducted emissions. for example, using a 4.7 h input capacitor, it is easy to calculate that an inductor of 200 nh will ensure that the input filter has a cut ? off frequency below 200 khz (low enough to attenuate the 2 mhz ripple). pcb layout recommendation as with any switching power supplies, there are some guidelines to follow to optimize the layout of the printed circuit board for the ncv890100. however, because of the high switching frequency extra care has to be taken. ? minimize the area of the power current loops: ? input capacitor ncv890100 switch inductor output capacitor return through ground ? freewheeling diode inductor output capacitor return through ground ? minimize the length of high impedance signals, and route them far away from the power loops: ? feedback trace ? comp trace ordering information device package shipping ? NCV890100MWTXG dfn8 with wettable flanks (pb ? free) 3000 / tape & reel ncv890100pdr2g soic ? 8 ep (pb ? free) 2500 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
ncv890100 http://onsemi.com 15 package dimensions soic ? 8 ep case 751ac issue b ?? ?? ?? h c 0.10 d e1 a d pin one 2 x 8 x seating plane exposed gauge plane 14 5 8 d c 0.10 a-b 2 x e b e c 0.10 2 x top view side view bottom view detail a end view section a ? a 8 x b a-b 0.25 d c c c 0.10 c 0.20 a a2 g f 1 4 58 notes: 1. dimensions and tolerancing per asme y14.5m, 1994. 2. dimensions in millimeters (angles in degrees). 3. dimension b does not include dambar protrusion. allowable dambar protrusion shall be 0.08 mm total in excess of the ?b? dimension at maximum material condition. 4. datums a and b to be determined at datum plane h. dim min max millimeters a 1.35 1.75 a1 0.00 0.10 a2 1.35 1.65 b 0.31 0.51 b1 0.28 0.48 c 0.17 0.25 c1 0.17 0.23 d 4.90 bsc e 6.00 bsc e 1.27 bsc l 0.40 1.27 l1 1.04 ref f 2.24 3.20 g 1.55 2.51 h 0.25 0.50 0 8 h aa detail a (b) b1 c c1 0.25 l (l1) pad e1 3.90 bsc a1 location *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* exposed pad 1.52 0.060 2.03 0.08 0.6 0.024 1.270 0.050 4.0 0.155 mm inches scale 6:1 7.0 0.275 2.72 0.107
ncv890100 http://onsemi.com 16 package dimensions dfn8, 3x3, 0.5p case 506by issue a ?? ?? ?? ?? ? ? ? ? ?? ?? ?? ?? ? ? ? ? 1 0.65 pitch 3.30 *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. recommended 8x dimensions: millimeters soldering footprint* notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b applies to plated terminal and is measured between 0.15 and 0.30mm from the terminal tip. 4. coplanarity applies to the exposed pad as well as the terminals. 5. for device opn containing w option, detail b alternate construction is not applicable. a b e d d2 e2 bottom view b e 8x 0.10 b 0.05 a c c k 8x note 3 2x 0.10 c pin one reference top view 2x 0.10 c a a1 (a3) 0.05 c 0.05 c c seating plane side view l 8x 14 5 8 dim min max millimeters a 0.80 1.00 a1 0.00 0.05 a3 0.20 ref b 0.25 0.35 d 3.00 bsc d2 2.20 2.40 e 3.00 bsc e2 1.40 1.60 e 0.65 bsc k 0.20 ??? l 0.20 0.40 l1 detail a l alternate constructions l detail b detail a l1 0.00 0.15 note 4 e/2 ?? ?? and are registered trademarks of semiconductor co mponents industries, llc (scillc). scillc owns the rights to a numb er of patents, trademarks, copyrights, trade secrets, and other intellectual property. a list ing of scillc?s product/patent coverage may be accessed at ww w.onsemi.com/site/pdf/patent ? marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/ or specifications can and do vary in different applications and actual performance may vary over time. all operating parame ters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or a uthorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in whic h the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or us e scillc products for any such unintended or unauthorized appli cation, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unin tended or unauthorized use, even if such claim alleges that scil lc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyrig ht laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 ncv890100/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

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